1. Field
This disclosure relates generally to integrated circuit memory, and more specifically, to a split-gate non-volatile memory cell having improved overlap tolerance and method therefor.
2. Related Art
A split-gate non-volatile memory cell includes a control gate and a select gate for controlling program, erase, and read operations. The control gate is used to control programming and erasing of the memory cell while the select gate is used to select when a memory cell is programmed or read. A prior art manufacturing process uses a three mask lithography process to form the two gates. Other processes may include the use of sacrificial features in addition to the three lithography processes. Alignment of each of the three masks is important. One prior art split-gate memory cell includes two polysilicon layers, where a portion of one polysilicon layer overlaps with a portion of the other layer. Any misalignment in the polysilicon layers can result in the control gate overlapping the select gate by too much overlap or too little. Too much overlap of the control gate over the select gate may minimize salicidation of the select gate causing failures due to high resistance of the select gate. Too little overlap, or no overlap, of the control gate over the select gate may cause poor isolation between the control gate and the select gate. The problem is worsened with scaling, resulting in reduced yields and decreased performance.
Therefore, what is needed is a split-gate memory cell, and a method for making a split-gate memory cell, that solves the above problems.